Radiation Hardened

Radiation in outer space consists of solar flares and solar winds, and the magnetosphere usually shields us from this; however, any electronic circuit in orbit would not last for more than a few minutes in space without hardening.

The Mars Odyssey Spacecraft measured high levels of radiation on Mars and the results the Martian environment poses extreme radiation hazard to crews of interplanetary missions. Ionising radiation causes cancers in humans, and destroys electronic circuitry in computers.

Digital circuits are very sensitive to errors at bit level. Damage to a single bit can result in the whole system crashing. Without radiation-hardening techniques, orbiting satellites would have a very short mission life. The term single event upset (SEU) describes this damage, when an energetic charged particle damages a memory cell of a metal oxide semiconductor (MOS) circuit within an IC.

MOS Memory Cell

MOS Memory Cell

At petervis.com, you get the best quality articles, and I go to great lengths to create these animated graphics. This MOS memory cell is capable of holding a single bit, either a one or zero.

When a pair of transistors switches ON -- shown in red -- they send a signal to the base junctions of the opposing pair of transistors, and consequently they switch ON sending a signal to the base junctions of the opposing pair. It is a basic flip-flop configuration; however, it is not radiation hardened. If an ionised particle were to hit just one of the MOS transistors, the whole circuit would no longer oscillate and the memory cell becomes dead.

Radiation Hardened MOS Memory Cell

Radiation Hardened MOS Memory Cell

The diagram above shows a typical radiation hardened memory cell. This cell can also store a single bit, either a one or zero, but uses double the number of transistors, compared to the previous example.

The PowerPC architecture consists of over 800,000 memory cells, which are SEU hardened. The complexity of hardening each memory cell increases the final cost of a RAD750.

Commonly known as the NASA Memory Cell, and the Whitaker cell, it was first utilised in the Reed-Solomon encoder of the Sky Lab space station.

The design relies on three fundamental concepts. First, the information is stored in two physically different places to provide data redundancy. If a particle strike destroys one memory cell then the data will still be available from the second cell.

Second, there must be a feedback mechanism from the non-damaged memory cell to initiate recovery of the lost data.

Third, the current induced by a particle strike has to flow from the n-type diffusion to p-type, thereby preventing short circuits.

The memory cell shown above there are two main circuits consisting of six transistors each. The top part of the circuit consists of p-channel transistors, whilst the lower part is made of n-channel transistors. The idea behind this is that a particle strike cannot upset both circuits simultaneously.

An advantage of this method is that we can achieve radiation hardening by design alone, whilst maintaining the same manufacturing processes.

Hardening each memory cell with additional transistors is expensive; hence, spacecraft generally tend to have just enough memory required for the job. The Space Shuttle computer had only 1 KB of memory, and it was made of ferrite core, because ferrite memory is robust and immune to space radiation.

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RAD750 Processor
PowerPC 750 Processor
Mars Rover Curiosity
Single Board Computer (SBC)
RAD750 Processor Architecture
Radiation Hardened
Mars Rover Power Supply