4 Bit Down Counter

Circuit Diagram

A 4-bit down counter is a digital counter circuit, which provides a binary countdown from binary 1111 to 0000. This circuit uses four D-type flip-flops, which are positive edge triggered. At each stage, the flip-flop feeds its inverted output (/Q) back into its own data input (D). However, it feeds its non-inverted output (Q) to the clock input (CK) of the following stage. This type of circuit operates in an asynchronous (ripple) manner because the flip-flop stages do not rely on a common clock pulse for timing. The operational speed of the counter depends upon the signal propagation through successive stages, rather than a common clock pulse as in synchronous circuits.

When RESET is applied on all the flip-flops simultaneously, their Q outputs become logic 0 state, and /Q outputs becomes logic 1 state. The /Q outputs are fed back into their own data inputs (D) and therefore all that they require is the rising edge of a clock pulse to transfer the data at input (D) to output Q.

Truth Table

DecimalQDQCQBQA
151111
141110
131101
121100
111011
101010
091001
081000
070111
060110
050101
040100
030011
020010
010001
000000

This type of circuit is useful in timer applications. A count down from decimal 15 to decimal 11 becomes simply a matter of looking for the 1-0-1-1 output, because at the decimal count of 11, the logic state of QA=1, QB=1, QC=0, and QD=1. In TTL digital circuits, logic 1 state, usually represents +5 V electrically, and we can use these outputs in many circuits for timer applications.