Divide by 5 Counter Circuit

A divide-by-5 counter, also known as MOD-5 counter, counts from 0 to 4, and on the 6th count it automatically resets. It is a three-bit counter requiring three D-type flip-flops. The solution is to start with a three-bit up counter and look for the output 5 (101 in binary), which we can feed into an AND gate. The output of the AND gate then provides the RESET control signal to the flip-flops. Therefore, the divide-by-5 number is the binary number used to generate the RESET signal to repeat the count sequence.

We start using a MOD-8 counter and modify it so that when the output reaches 5, which is binary 101, all the flip-flops will be reset. To generate the RESET control signal all one requires is to feed the 2 power 0, and 2 power2 outputs to an AND gate. When both inputs are logic 1, the AND gate produces the RESET signal.

Notice that the inverted output (/Q) of the previous stage feeds the clock input (CK) of the successive stage, in a ripple fashion.

Notice that we are feeding the inverted output (/Q) back to the data input (D) to make a frequency divider.