How Does 555 Timer Work

The trick to understanding how the 555 timer works, is to begin by understanding the SR flip-flop operation logic. Asserting the SET function makes Q=1 and /Q=0. This state remains until the assertion of the RESET function, which makes Q=0 and /Q=1. However, note that you cannot assert both SET and RESET functions simultaneously, as this is a forbidden condition.

The logic which drives the SET and RESET functions comes from the comparator outputs. Each comparator is a differential op amp with two inputs, and they simply compare their inputs by subtracting them, and feeding the result to the output. Inside the IC package, there are three equal value resistors forming a potential divider network between the voltage rails. The threshold input is always compared with 2/3 of Vcc, and its output controls the RESET function, whilst the trigger input is always compared with 1/3 of Vcc and its output controls the SET function.

Notice that the threshold input connects to the non-inverting input of its comparator, whilst the trigger input connects to the inverting input of its comparator. This way, the trigger value has to fall to or below 1/3 Vcc reference for asserting SET, whilst the threshold input has to rise to or above 2/3 Vcc reference for asserting RESET. The engineers designed it like this purposefully, where one has to rise and the other has to fall, to prevent the triggering of SET and RESET functions simultaneously.

So to recap, when the trigger input falls to or below 1/3 Vcc, the comparator output asserts the SET function, and the flip-flop output Q is logic 1. When the threshold input rises to or above 2/3 Vcc, the comparator asserts the RESET function and the output Q is logic 0.

In the following pages of this article, I have designed a great animation of the 555 timer in astable mode showing the charging and discharging cycles of the capacitor.

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