Phase Lock loop (PLL) LM565 Circuit

A Phase Lock Loop (PLL) is an electronic circuit, which locks the phase of the input signal with that of the output by keeping them synchronised. It achieves this through a closed loop feedback mechanism that compares the input signal with the output and makes the necessary corrections so that the phase remains synchronous.

The LM565 is a PLL IC, which may not be readily available; however, an alternative compatible IC is the NTE989. The values of the components may have changed during design, so please use the full schematic in the final draft of the circuit diagram. The job of a PLL is to track an incoming frequency and match the phase precisely. However, in this circuit the feedback loop has a divided-by-16 counter, which returns the feedback signal that is 16 fold less. As a result, the phase lock will attempt to compensate and multiply the incoming frequency 16 fold.

If the input signal changes, the phase detector will recognise the change in frequency and force the VCO to change the output accordingly, such that the output is equal to the new input frequency, thereby eliminating the error value from the phase comparator.

The free running frequency "ƒc" occurs when the PLL has no lock or if there is no input signal, or if the signal is outside the lock range. The range of frequencies over which the PLL will track an input signal and remain locked is the lock frequency. This range is above and below the VCO free running frequency. The PLL will track and lock to any input frequency in this range. If the input signal happens to be out of this lock range then the PLL will not be able to track it.

As the input frequency gets closer to within the lock range, the PLL will jump into a locked condition. As soon as the input frequency gets close to the VCO frequency, a condition known as capturing occurs. During this time, the PLL remains locked, and tracks any further changes to the input frequency. The range of frequencies over which a PLL can capture a signal is the capture range, and just as the lock range, the capture range centres around the free running frequency. Since the PLL captures within a narrow band, it behaves as a band-pass filter.

Calculating Input Range

An engine turns at a maximum of 7500 revolutions per minute, and a minimum of 500 revolutions per minute. For one rotation of the engine, the Hall sensor produces four pulses.

The maximum frequency is therefore:

4 × (7500) / 60 = 500 pulses per second or 500 Hz

The minimum frequency is therefore:

4 × (500) / 60 = 33.33 pulses per second or 33.33 Hz

Free Running Frequency

The free running frequency "ƒc" is centred around the input frequency range as shown in the diagram.

Calculating Ro × Co

ƒc = 0.3 / (Ro × Co)

This formula provides the values of resistor "Ro" and capacitor "Co", based on the centre frequency "ƒc".

Since we require the centre frequency "ƒc" to be 266.665

Ro × Co = 0.001125007

If we set Co to a value of 1 µF then Ro would have to be 1125.007-ohms, which can be made from a 1000 Ω fixed resistor, and 220 Ω preset in series.

LM565 PLL Circuit Diagram

Therefore, in the circuit above, pin 9 (TC) has a 1 µF capacitor, and pin 8 (TR) has 1 kΩ resistor, and 220 Ω preset, in series. These will make sure that the PLL can keep a lock within our desired frequency range.

The full calculation is much lengthier; however, I have shortened it to make it easy to understand.

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