D Type Flip Flop

The D-type flip-flop (D for Data), also known as a rising edge triggered RS flip-flop with one input, is one of the simplest forms of flip-flop circuits used in digital electronics. The 4013 is a typical electronic component used for experimenting with the operation of this device. This device usually performs a logic function in the form of a latch, which you can think of as a simple memory to hold 1-bit. We usually use this device to torture GCSE students who are looking for a simple explanation of how it operates. It has other multi-functions as well, and depending upon the circuit configuration, it makes a great register application, or a toggle switch application. However, before we go into the advanced circuits, we need to understand its basic pin functions.

According to the JDEC specifications, the abbreviation and full name of the pin designations are as follows.

A D-type flip-flop usually has one data input pin marked "D", and two outputs at "D" and "/D". There is usually pin "S" to SET the device, and pin "R" to RESET the device. The clock signal "CK" is one of the most important inputs, which makes the whole component work.

When you think about it, SET, and RESET, are control functions of the device. Data is the input, and "Q", and "/Q" are outputs. This device has two outputs, which always exhibit opposing logic states. If "Q"=1, then "/Q"=0, and if "Q"=0, then "/Q"=1.

SET S and RESET R

SET and RESET are usually active high pins, which means that when you wish to activate their functions, you simply need to set them to logic 1 state, with a momentary connection to the positive supply rail, otherwise known as +5 V or +9 V depending upon your circuit. Remember, that in this type of component SET and RESET pins cannot both be logic 1 at the same time. It is important to understand that RESET overrides DATA and CLOCK inputs. When RESET is logic 1, it overrides the input "D", and clock "CK" logic states, and forces the output "Q" to become logic 0.

Rising Edge Triggered

The CLOCK is the most important factor to make this device work. In sequential logic, every operation occurs in a timely fashion controlled by the clock pulse. In computer systems, there is usually a fast train of clock pulses generated by an oscillator; however, this is not always required. A slow change in transition from low to high is good enough, and you could even use a simple manual non-locking switch in your circuits.

If you had a non-locking switch, it could feed the supply rail voltage to the clock input pin "CK", when required. When you press the switch, this causes a positive-going transition part -- also known as leading edge or rising edge -- from low to high, and the value at the input "D" transfers to output "Q". When you let go of the switch, this is the negative-going transition part – also known as the trailing edge -- of the clock pulse, which locks the value at output "Q".

The hold time signified by the dotted part in the timing diagram is actually not that important because this IC looks only for a change in state at the leading edge, or at the trailing edge of the pulse. Therefore it is said to be an edge-triggered device.

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