Rising Edge Triggered D Flip Flop

A rising edge triggered d flip-flop is one where the logic level present at the input D transfers to Q on the rising edge of the clock pulse. If we set the input at D to logic 1, and the initial state of the flip-flop is in reset condition, with Q initially logic 0. What would be the output at Q when we feed a clock pulse at CK?

The graph should show an output of logic 1 at the rising edge of the clock pulse.

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